Makefile -overriding variables

To override the variables defined in the makefile from the command line,this will do
make CFLAGS='-g -O' .This will override the assignment of CFLAGS in the makefile. the simple assignment in the makefile will be ignored. Found this out from [1]

There is a way to override this assignment in the command line using the override directive
If a variable has been set with a command argument , then ordinary assignments in the makefile are ignored. If you want to set the variable in the makefile even though it was set with a command argument, you can use an override directive.
Syntax:
In makefile use

override variable = value

Further details in [2]

References:
[1] http://www.gnu.org/software/autoconf/manual/make/Overriding.html
[2]
http://www.gnu.org/software/autoconf/manual/make/Override-Directive.html#Override-Directive

alternate makefile name

The way to specify the name of the makefile is with the `-f' or `--file' option (`--makefile' also works). For example, `-f altmake' says to use the file `altmake' as the makefile.

If you use the `-f' flag several times and follow each `-f' with an argument, all the specified files are used jointly as makefiles.

If you do not use the `-f' or `--file' flag, the default is to try `GNUmakefile', `makefile', and `Makefile', in that order, and use the first of these three which exists or can be made

Makefile wildcards!

Blogging after a very long gap!

There came a need to compile all the c files in directory.Learnt that i need to make use of wildcards

a makefile to compile all C source files in the directory and then link them together could be written as follows:

objects := $(patsubst %.c,%.o,$(wildcard *.c))

foo : $(objects)
      cc -o foo $(objects)

and a few pointers as usual

[1] http://www.metalshell.com/view/tutorial/120/
[2] http://theory.uwinnipeg.ca/localfiles/infofiles/make/make_25.html
[3] http://www.gnu.org/software/make/manual/make.html